1. Technical Field
The invention relates generally to yield modeling, and more particularly, to a method, system and program product for dynamically determining a yield expectation during manufacturing of a lot of a product.
2. Background Art
Accurate yield expectation determination of a lot of integrated circuits (ICs) is a significant but difficult task in an IC manufacturing facility. For example, vertically integrated semiconductor fabrication of a forty-plus mask level microprocessor has a cycle time of approximately 120 days from a wafer start to shipping a tested module to the customer. Due to this cycle time, there is an uncertainty in projecting a yield to the customer. Overestimating yield will cause a supply shortfall and underestimating yield will result in inventory and lost revenue. IC fabricators presently use yield models based on critical area, circuit count, defect density data, and/or electrical test data to project yields. For example, U.S. Pat. No. 6,610,550, entitled “Methods and Apparatus for Correlating Error Model With Defect Data” discloses one of these methods. For semiconductor fabrication at the 90 nm node, yield is highly variable within a wafer lot and lot-to-lot, dependant on not only defect density but systematic detractors, wafer substrate, tool variations and process changes. This creates a large uncertainty in the yield expectation (e.g., +/−50%) making it difficult to balance customer serviceability and fabricator revenue, especially for an IC fabricator having multiple part numbers and/or multiple customers.
In view of the foregoing, there is a need in the art for an improved way to determine a yield expectation in an IC manufacturing facility that does not suffer from one or more of the problems of the related art.